Negative voltage wordline methods and systems
US10832778B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2019 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Jun 28, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3468
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A methodology and structure for driving a selected wordline to a negative voltage without the need for a negative wordline voltage generator. The methodology includes the step of boosting a non-selected wordline to a first positive voltage. The methodology proceeds with holding a selected wordline, which is adjacent to and capacitively coupled with the non-selected wordline, at zero voltage. The methodology continues with floating the selected wordline. The methodology proceeds with driving the non-selected wordline to a lower voltage to shift the selected wordline to less than zero volts due to capacitance effects. The methodology continues with the step of accelerating charge loss in a defective memory cell connected to the selected wordline while at a negative voltage during a soft erase operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.