Selective recessing to form a fully aligned via
US10832952B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 21, 2018 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Jun 21, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2221/1021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device having a vertical metal line interconnect (via) fully aligned to a first direction of a first interconnect layer and a second direction of a second interconnect layer in a selective recess region by forming a plurality of metal lines in a first dielectric layer; and recessing in a recess region first portions of the plurality of metal lines such that top surfaces of the first portions of the plurality of metal lines are below a top surface of the first dielectric layer; wherein a non-recess region includes second portions of the plurality of metal lines that are outside the recess region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.