Precision alignment of multi-chip high density interconnects
US10833051B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2019 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Jan 24, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/37001
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Place a first semiconductor chip onto an alignment carrier with protrusions of the semiconductor chip inserted into corresponding cavities of the alignment carrier, so that the protrusions and cavities locate the semiconductor chip with interconnect contacts overlying a window that is formed through the alignment carrier. Place a second semiconductor chip onto the alignment carrier with protrusions of the second semiconductor chip inserted into cavities of the alignment carrier, so that the protrusions and cavities locate the second semiconductor chip with interconnect contacts of the second semiconductor chip adjacent to the interconnect contacts of the first semiconductor chip and overlying the window. Fasten the semiconductor chips to the alignment carrier. Touch contacts of a interconnect bridge against the interconnect contacts of the first and second semiconductor chips by putting the interconnect bridge through the window.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.