Patent · US Active

SOI wafers and devices with buried stressor

US10833194B2 · kind B2 · utility

1Cited by
32References
5Claims
0Family size

Assignee

Inventors

Key dates

Filing dateFeb 22, 2019
Grant dateNov 10, 2020
Priority date—
Expiry dateMay 3, 2039

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D86/201
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A semiconductor structure includes a layer arrangement consisting of, in sequence, a semiconductor-on-insulator layer (SOI) over a buried oxide (BOX) layer over a buried stressor (BS) layer with a silicon bonding layer (BL) intervening between the BOX and the BS layers. The semiconductor structure may be created by forming the BS layer on a substrate of a first wafer; growing the BL layer at the surface of the BS layer; wafer bonding the first wafer to a second wafer having a silicon oxide layer formed on a silicon substrate such that the silicon oxide layer of the second wafer is bonded to the BL layer of the first wafer, and thereafter removing a portion of the silicon substrate of the second wafer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.