Inventor · Santa Monica, CA, US

Paul A. Clifton

57Patents
10h-index
14Co-inventors
75Inventor score

Filing activity: Apr 15, 2003 → Sep 26, 2023

Most-cited inventions

PatentTitleAreaCited byStatus
US7700416B1 Tensile strained semiconductor on insulator using elastic edge relaxation and a sacrificial stressor layer Emerging Cross-Sectional Technologies 35 Active
US8212336B2 Field effect transistor source or drain with a multi-facet surface Electricity 21 Active
US7338834B2 Strained silicon with elastic edge relaxation Electricity 20 Active
US8731017B2 Tensile strained semiconductor photon emission and detection devices and integrated photonics system Electricity 19 Active
US8263467B2 Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor Electricity 16 Active
US8658523B2 Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s) Electricity 15 Active
US7851325B1 Strained semiconductor using elastic edge relaxation, a buried stressor layer and a sacrificial stressor layer Electricity 14 Active
US7816240B2 Method for making semiconductor insulated-gate field-effect transistor having multilayer deposited metal source(s) and/or drain(s) Electricity 13 Active
US9036672B2 Tensile strained semiconductor photon emission and detection devices and integrated photonics system Electricity 11 Active
US9362376B2 Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers Electricity 10 Active
US9270083B2 Tensile strained semiconductor photon emission and detection devices and integrated photonics system Electricity 9 Active
US7902029B2 Process for fabricating a self-aligned deposited source/drain insulated gate field-effect transistor Electricity 8 Expired
US8395213B2 Strained semiconductor using elastic edge relaxation of a stressor combined with buried insulating layer Electricity 7 Active
US9620611B1 MIS contact structure with metal oxide conductor Electricity 7 Active
US7972916B1 Method of forming a field effect transistors with a sacrificial stressor layer and strained source and drain regions formed in recesses Electricity 5 Active
US8361868B2 Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation Electricity 5 Active
US7977147B2 Strained silicon with elastic edge relaxation Electricity 5 Active
US10170627B2 Nanowire transistor with source and drain induced by electrical contacts with negative schottky barrier height Electricity 5 Active
US10833199B2 Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height Electricity 4 Active
US7612365B2 Strained silicon with elastic edge relaxation Electricity 3 Active
US10193307B2 Tensile strained semiconductor photon emission and detection devices and integrated photonics system Electricity 3 Active
US10505047B2 Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height Electricity 3 Active
US8361867B2 Biaxial strained field effect transistor devices Electricity 3 Active
US9059201B2 Transistor with longitudinal strain in channel induced by buried stressor relaxed by implantation Electricity 3 Active
US10147798B2 MIS contact structure with metal oxide conductor Electricity 3 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.