Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US10833199B2 · kind B2 · utility
4Cited by
202References
34Claims
0Family size
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Key dates
| Filing date | Nov 22, 2019 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Nov 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/647
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
A nanowire transistor includes undoped source and drain regions electrically coupled with a channel region. A source stack that is electrically isolated from a gate conductor includes an interfacial layer and a source conductor, and is coaxially wrapped completely around the source region, extending along at least a portion of the source region. A Schottky barrier between the source conductor and the source region is a negative Schottky barrier and a concentration of free charge carriers is induced in the semiconductor source region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.