Current compliance layers and memory arrays comprising thereof
US10833263B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 7, 2020 |
| Grant date | Nov 10, 2020 |
| Priority date | — |
| Expiry date | Jan 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/76
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Provided are novel compositions of current compliance layers (CCLs) as well as novel methods of fabricating such CCLs and novel architectures of arranging CCLs and memory cells in memory arrays. A CCL may comprise one of sulfur (S), selenium (Se), and tellurium (Te). The CCL may further comprise one of germanium (Ge) and silicon (Si). CCLs may be fabricated as amorphous structure and remain amorphous when heated to 400° C. or 450° C. and above. In some embodiments, CCLs have crystallization temperatures of greater than 400° C. and, in some embodiments, glass transition temperatures of greater than 400° C. CCLs may be fabricated using atomic layer deposition (ALD) as a nanolaminate of layers having different compositions. The composition, number, and arrangement of the layers in the nanolaminate is specifically selected to yield a desired composition of CCL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.