Programming of memory cell having gate capacitively coupled to floating gate
US10838652B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2018 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Feb 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device with memory cells each including source and drain regions with a channel region there between, a floating gate over a first channel region portion, a select gate over a second channel region portion, a control gate over the floating gate, and an erase gate over the source region. Control circuitry is configured to, for one of the memory cells, apply a first pulse of programming voltages that includes a first voltage applied to the control gate, perform a read operation that includes detecting currents through the channel region for different control gate voltages to determine a target control gate voltage using the detected currents that corresponds to a target current through the channel region, and apply a second pulse of programming voltages that includes a second voltage applied to the control gate that is determined from the first voltage, a nominal read voltage and the target voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.