Semiconductor memory
US10839913B2 · kind B2 · utility
3Cited by
1References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 11, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Sep 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory includes: a first bit line; a first select transistor having a first terminal connected to the first bit line; a first memory cell connected to a second terminal of the first select transistor; a circuit connected to the first bit line and applying an erase voltage to be applied to the first memory cell to the bit line via the first terminal and the second terminal; and a diode connected to the first bit line and the first circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.