Patent · US Active

Memory disturb detection

US10839922B2 · kind B2 · utility

4Cited by
11References
24Claims
0Family size

Assignee

Inventors

Key dates

Filing dateMay 26, 2018
Grant dateNov 17, 2020
Priority date
Expiry dateAug 9, 2038

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG11C2029/0411
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

An apparatus includes an array of memory cells comprising a first sub-block and a second sub-block electrically coupled by a channel. The apparatus also includes a measurement circuit configured to take a first measurement of a first sub-block of memory cells at a first offset threshold and a second measurement of the first sub-block of memory cells at a second offset threshold. The apparatus further includes a detection circuit configured to detect a disturb condition of the first sub-block based on at least one of the first measurement and the second measurement, and to initiate data maintenance in response to the disturb condition of the first sub-block.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.