Semiconductor package structure and method for manufacturing the same
US10840219B2 · kind B2 · utility
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19Claims
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Key dates
| Filing date | Jun 6, 2019 |
| Grant date | Nov 17, 2020 |
| Priority date | — |
| Expiry date | Jun 9, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package structure includes: (1) a first substrate; (2) at least one first semiconductor element attached to the first substrate; and (3) a second substrate including a plurality of thermal vias and a plurality of conductive vias, wherein one end of each of the thermal vias directly contacts the first semiconductor element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.