Automatic definition and extraction of functional coverage metric for emulation-based verification
US10846455B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2019 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Mar 8, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/331
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of verifying a circuit design, includes, in part, identifying a first groups of signals associated with the circuit, selecting a signal sampling window depth, performing a first verification of the circuit using a first test bench adapted to cause transitions in the first group of signals, storing values of the signals in the first group during each of the cycles defined by the sapling window depth to generate a first functional coverage, performing a second verification of the circuit design using a second test bench to generate a second functional coverage, comparing the second functional coverage to the first functional coverage, and automatically generating one or more cover property statements if the second functional coverage is less than the first functional coverage. The one or more cover property statements cause the second functional coverage to become equal to or greater than the first functional coverage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.