Eduard Cerny
12Patents
4h-index
23Co-inventors
60Inventor score
Filing activity: Jun 16, 1998 → Jun 21, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6363520B1 | Method for testability analysis and test point insertion at the RT-level of a hardware development language (HDL) specification | Physics | 52 | Expired |
| US7076753B2 | Method and apparatus for solving sequential constraints | Physics | 15 | Expired |
| US7797123B2 | Method and apparatus for extracting assume properties from a constrained random test-bench | Physics | 10 | Active |
| US7454727B1 | Method and Apparatus for Solving Sequential Constraints | Physics | 7 | Active |
| US8527921B2 | Constrained random simulation coverage closure guided by a cover property | Physics | 3 | Active |
| US11501050B1 | Analog mixed-signal assertion-based checker system | Physics | 2 | Active |
| US10846455B2 | Automatic definition and extraction of functional coverage metric for emulation-based verification | Physics | 2 | Active |
| US8448109B1 | Vector evaluation of assertions | Physics | 1 | Active |
| US9626468B2 | Assertion extraction from design and its signal traces | Physics | 1 | Active |
| US11544435B1 | On-the-fly computation of analog mixed-signal (AMS) measurements | Physics | 0 | Active |
| US10831956B2 | Efficient execution of alternating automaton representing a safety assertion for a circuit | Physics | 0 | Active |
| US11188695B2 | Unified functional coverage and synthesis flow for formal verification and emulation | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.