Write data processing circuits and methods associated with computational memory cells
US10847213B1 · kind B1 · utility
13Cited by
270References
15Claims
0Family size
Assignee
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Key dates
| Filing date | Aug 23, 2018 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Aug 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0944
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A write data processing apparatus and method associated with computational memory cells formed as a memory/processing array provides the ability to shift data between adjacent bit lines in each section of the memory/processing array or the same relative bit lines in adjacent sections of the memory/processing array. The memory/processing array has one or more sections and each section has its own unique set of “n” bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.