Interconnect assemblies with through-silicon vias and stress-relief features
US10847442B2 · kind B2 · utility
1Cited by
4References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 24, 2014 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Feb 15, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device in accordance with some embodiments includes a substrate structure and a conductive interconnect extending through at least a portion of the substrate structure. The conductive interconnect can include a through-silicon via and a stress-relief feature that accommodates thermal expansion and/or thermal contraction of material to manage internal stresses in the semiconductor device. Methods of manufacturing the semiconductor device in accordance with some embodiments includes removing material of the conductive interconnect to form the stress-relief gap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.