Semiconductor package with in-package compartmental shielding and fabrication method thereof
US10847480B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Jan 1, 2019 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Jan 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a substrate. At least a high-frequency chip and a circuit component susceptible to high-frequency interference are disposed on a top surface of the substrate. A first ground ring is disposed on the substrate surrounding the high-frequency chip. A first metal-post reinforced glue wall is disposed on the first ground ring surrounding the high-frequency chip. A second ground ring is disposed on the top of the substrate surrounding the circuit component. A second metal-post reinforced glue wall is disposed on the second ground ring surrounding the circuit component. A molding compound covers at least the high-frequency chip and the circuit component. A conductive layer is disposed on the molding compound and is coupled to the first metal-post reinforced glue wall and/or the second metal-post reinforced glue wall.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.