Three-dimensional memory devices having through stair contacts and methods for forming the same
US10847539B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 4, 2019 |
| Grant date | Nov 24, 2020 |
| Priority date | — |
| Expiry date | Apr 11, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of three-dimensional (3D) memory devices having through stair contacts (TSCs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including a plurality of interleaved dielectric layers and sacrificial layers is formed on a substrate. A staircase structure is formed on one side of the dielectric stack. A dummy hole extending vertically through the staircase structure and reaching the substrate is formed. A spacer having a hollow core is formed in the dummy hole. A TSC in contact with the substrate is formed by depositing a conductor layer in the hollow core of the spacer. The TSC extends vertically through the staircase structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.