Patent · US Active

Test structures for measuring silicon thickness in fully depleted silicon-on-insulator technologies

US10852337B2 · kind B2 · utility

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3References
8Claims
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Key dates

Filing dateJun 1, 2017
Grant dateDec 1, 2020
Priority date—
Expiry dateAug 8, 2037

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG01B2210/56
  • WIPO fieldMeasurement
  • WIPO sectorInstruments

Abstract

Described are test structures and methods for measuring silicon thickness in fully depleted silicon-on-insulator technologies.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.