Patent · US Active

Read assist circuitry for memory applications

US10854280B2 · kind B2 · utility

1Cited by

0References

19Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Abhairaj Singh · Chandigarh, IN
Vivek Asthana · Greater Noida, IN
Monu Rathore · Delhi, IN
Ankur Goel · Bengaluru, IN
Nikhil Kaushik · Noida, IN
Rachit Ahuja · Noida, IN
Rahul Mathur · Austin, US
Bikas Maiti · Austin, US
Yew Keong Chong · Austin, US

Key dates

Filing date	Aug 30, 2017
Grant date	Dec 1, 2020
Priority date	—
Expiry date	Oct 23, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG11C11/418
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to an integrated circuit having a wordline driver coupled to a bitcell via a wordline. The integrated circuit may include a read assist transistor coupled to the wordline between the wordline driver and the bitcell. While activated, the read assist transistor may generate an adaptive underdrive on the wordline, the level of which depends on the process, temperature and voltage of operation of the memory, when the wordline is selected and driven by the wordline driver.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.