Computational memory cell and processing array device with ratioless write port
US10854284B1 · kind B1 · utility
15Cited by
264References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 7, 2020 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Feb 7, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computational memory cell and processing array have a ratioless write port so that a write to the memory cell does not need to overcome the drive strength of a PMOS transistor that is part of the storage cell of the memory cell. The computational memory cell also may have a second read port that has an isolation circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.