Method for reducing reactive ion etch lag in low K dielectric etching
US10854453B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 11, 2018 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Jun 11, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/31144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A substrate processing technique is described herein for etching layers, such as dielectric layers, and more particularly low k dielectric layers in a manner that minimizes etch lag effects. Multiple etch processes are utilized. A first etch process may exhibit etch lag. A second etch process is a multi-step process that may include a deposition sub-step, a purge sub-step and an etch sub-step. The second etch process may exhibit inverse etch lag. The second etch process may be a cyclic process which performs the deposition, purge and etch sub-steps a plurality of times. The second etch process may be an atomic layer etch based process, and more particularly a quasi-atomic layer etch. The combination of the first etch process and the second etch process may provide the desired net effect for the overall etch lag when etching the dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.