Methods of lowering wordline resistance

US10854511B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• Yihong Chen · San Jose, US
• Yong Wu · Sunnyvale, US
• Chia Cheng Chin · Fremont, US
• Xinliang Lu · Fremont, US
• Srinivas Gandikota · Santa Clara, US
• Ziqing Duan · Sunnyvale, US
• Abhijit Basu Mallick · Palo Alto, US

Key dates

• Filing date: Jun 5, 2018
• Grant date: Dec 1, 2020
• Expiry date: Jun 5, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C8/14
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods for forming 3D-NAND devices comprising recessing a poly-Si layer to a depth below a spaced oxide layer. A liner is formed on the spaced oxide layer and not on the recessed poly-Si layer. A metal layer is deposited in the gaps on the liner to form wordlines.