Supportive layer in source/drains of FinFET devices
US10854715B2 · kind B2 · utility
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10References
20Claims
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Assignee
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Key dates
| Filing date | Apr 13, 2018 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | Apr 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An embodiment is a semiconductor structure. The semiconductor structure includes a fin on a substrate. A gate structure is over the fin. A source/drain is in the fin proximate the gate structure. The source/drain includes a bottom layer, a supportive layer over the bottom layer, and a top layer over the supportive layer. The supportive layer has a different property than the bottom layer and the top layer, such as a different material, a different natural lattice constant, a different dopant concentration, and/or a different alloy percent content.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.