Patent · US Active

Method for producing IGBT with dV/dt controllability

US10854739B2 · kind B2 · utility

1Cited by
3References
22Claims
0Family size

Assignee

Inventors

Key dates

Filing dateApr 1, 2020
Grant dateDec 1, 2020
Priority date
Expiry dateApr 1, 2040

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D64/519
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A power semiconductor device includes: a drift region; a plurality of IGBT cells each having a plurality of trenches extending into the drift region along a vertical direction and laterally confining at least one active mesa which includes an upper section of the drift region; and an electrically floating barrier region of an opposite conductivity type as the drift region and spatially confined, in and against the vertical direction, by the drift region. A total volume of all active mesas is divided into first and second shares, the first share not laterally overlapping with the barrier region and the second share laterally overlapping with the barrier region. The first share carries the load current at least within a range of 0% to 100% of a nominal load current. The second share carries the load current if the load current exceeds at least 0.5% of the nominal load current.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.