NAND memory arrays, devices comprising semiconductor channel material and nitrogen, and methods of forming NAND memory arrays
US10854747B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 15, 2019 |
| Grant date | Dec 1, 2020 |
| Priority date | — |
| Expiry date | May 15, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/3211
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Some embodiments include device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen-containing material directly against the semiconductor channel material and on an opposing side of the semiconductor channel material from the dielectric region. Some embodiments include a device having a gate spaced from semiconductor channel material by a dielectric region, and having nitrogen within at least some of the semiconductor channel material. Some embodiments include a NAND memory array which includes a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. Charge-storage material is between the channel material and the wordline levels. Dielectric material is between the channel material and the charge-storage material. Nitrogen is within the channel material. Some embodiments include methods of forming NAND memory arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.