Processing method for package substrate
US10861716B2 · kind B2 · utility
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4Claims
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Key dates
| Filing date | Mar 8, 2019 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Mar 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A processing method for a package substrate in which a plurality of device chips on a wiring base material are sealed with a sealant includes a through-hole forming step of forming a through-hole in the package substrate so as to have a predetermined positional relation to a scheduled division line and a segmentation step of performing alignment with reference to the through-hole and segmenting the package substrate along the scheduled division line from the sealant side to segment the package substrate into individual packages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.