Memory device with bitline noise suppressing scheme
US10861787B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 7, 2019 |
| Grant date | Dec 8, 2020 |
| Priority date | — |
| Expiry date | Aug 7, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include an integrated memory having a first bitline coupled with a first set of memory cells, and having a second bitline coupled with a second set of memory cells. The first and second bitlines are comparatively coupled through a sense amplifier. A first noise suppression line is adjacent to a region of the first bitline and extends parallel to the region of the first bitline. The first noise suppression line is electrically connected with one of the first and second bitlines and not with the other of the first and second bitlines. A second noise suppression line is adjacent to a region of the second bitline and extends parallel to the region of the second bitline. The second noise suppression line is electrically connected with the other of the first and second bitlines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.