Data latch circuit and semiconductor memory device
US10867641B2 · kind B2 · utility
0Cited by
5References
10Claims
0Family size
Assignee
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Key dates
| Filing date | Mar 18, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Mar 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data latch circuit includes a first n-channel transistor and a first p-channel transistor. A gate of the first n-channel transistor and a gate of the first p-channel transistor are a common gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.