Reset before write architecture and method
US10867665B1 · kind B1 · utility
2Cited by
5References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2018 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Feb 14, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/229
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM bit-cell with independent write and read ports and an architecture utilizing a feedback loop from the read port to the write port of half-selected bit-cells. This guarantees absolute data retention of all SRAM bit-cells not fully selected for write operation across a wide range of supply voltage spanning from the nominal voltage of a process to a sub-threshold range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.