Double plug method for tone inversion patterning
US10867854B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jan 8, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Jan 8, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/67109
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Double plug methods for tone inversion patterning are described. In an embodiment, a method may include receiving the substrate having a multi-line layer formed thereon. Such a method may also include forming a patterned recess in the multi-line layer, the recess defining an inversion pattern on the substrate. The methods may also include depositing a first plug layer in the patterned recess using a first deposition process. Additionally, the methods may include depositing a second plug layer in the patterned recess using a second deposition process, the second deposition process being different from the first deposition process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.