Through silicon via fabrication
US10867855B2 · kind B2 · utility
2Cited by
0References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 13, 2019 |
| Grant date | Dec 15, 2020 |
| Priority date | — |
| Expiry date | Jun 14, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53238
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One or more embodiments are directed to establishing electrical connections through silicon wafers with low resistance and high density, while at the same time maintaining processability for further fabrication. Such connections through silicon wafers enable low resistance connections from the top side of a silicon wafer to the bottom side of the silicon wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.