Patent · US Active

Three-dimensional memory devices and fabricating methods thereof

US10868033B2 · kind B2 · utility

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2References
10Claims
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Assignee

Inventors

Key dates

Filing dateDec 14, 2018
Grant dateDec 15, 2020
Priority date
Expiry dateDec 14, 2038

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10B43/35

Abstract

A method for forming a gate structure of a 3D memory device is provided. The method comprises: forming, on a substrate, an alternating dielectric stack including a plurality of dielectric layer pairs, each of the plurality of dielectric layer pairs comprising a first dielectric layer and a second dielectric layer different from the first dielectric layer; forming a slit penetrating vertically through the alternating dielectric stack and extending in a horizontal direction; removing the plurality of second dielectric layers in the alternating dielectric stack through the slit to form a plurality of horizontal trenches; forming a gate structure in each of the plurality of horizontal trenches; forming a spacer layer on sidewalls of the slit to cover the gate structures, wherein the spacer layer has a laminated structure; and forming a conductive wall in the slit, wherein the conductive wall is insulated from the gate structures by the spacer layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.