Structure of memory device and fabrication method thereof

US10868197B1 · kind B1 · utility

Assignee

• UNITED MICROELECTRONICS CORP. · TW

Inventors

• Liang Yi · Singapore, SG
• Zhiguo Li · Hangzhou City, CN
• Chi Ren · Wenzhou, CN

Key dates

• Filing date: Jun 25, 2019
• Grant date: Dec 15, 2020
• Expiry date: Jun 25, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D30/696

Abstract

A structure of a memory device and a fabrication method thereof are provided. The structure of the memory device includes a tunneling layer disposed on a substrate. A first oxide/nitride/oxide (ONO) layer is disposed on the substrate abutting to the tunneling layer. A floating gate is disposed on the tunneling layer, wherein a side portion of the floating gate is also disposed on the first ONO layer. A second ONO layer is disposed on the floating gate. A control gate is disposed on the second ONO layer. An isolation layer is disposed on first sidewalls of the floating gate and sidewalls of the control gate. An erase gate is disposed on the first ONO layer, wherein the erase gate is isolated from the floating gate and the control gate by the isolation layer.