Method and system for latch-up prevention
US10872190B2 · kind B2 · utility
3Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2019 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | Jan 31, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2117/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit design method includes receiving an integrated circuit design, and determining a floor plan for the integrated circuit design. The floor plan includes an arrangement of a plurality of functional cells and a plurality of tap cells. Potential latchup locations in the floor plan are determined, and the arrangement of at least one of the functional cells or the tap cells is modified based on the determined potential latchup locations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.