Image processor with high throughput internal communication protocol
US10872393B2 · kind B2 · utility
0Cited by
3References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 15, 2017 |
| Grant date | Dec 22, 2020 |
| Priority date | — |
| Expiry date | May 27, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor is described. The processor includes a network. A plurality of processing cores are coupled to the network. The processor includes a transmitter circuit coupled to the network. The transmitter circuit is to transmit output data generated by one of the processing cores into the network. The transmitter circuit includes control logic circuitry to cause the transmitter circuit to send a request for transmission of a second packet of output data prior to completion of the transmitter circuit's transmission of an earlier first packet of output data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.