Qiuling Zhu
31Patents
6h-index
14Co-inventors
58Inventor score
Filing activity: Jan 16, 2014 → Aug 24, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US9772852B2 | Energy efficient processor core architecture for image processor | Electricity | 10 | Active |
| US9756268B2 | Line buffer unit for image processor | Electricity | 8 | Active |
| US9749548B2 | Virtual linebuffers for image signal processors | Physics | 8 | Active |
| US9769356B2 | Two dimensional shift array for image processor | Physics | 7 | Active |
| US10277833B2 | Virtual linebuffers for image signal processors | Physics | 6 | Active |
| US10321077B2 | Line buffer unit for image processor | Electricity | 6 | Active |
| US9965824B2 | Architecture for high performance, power efficient, programmable image processing | Emerging Cross-Sectional Technologies | 3 | Active |
| US10204396B2 | Compiler managed memory for image processor | Physics | 3 | Active |
| US10291813B2 | Sheet generator for image processor | Physics | 2 | Active |
| US10516833B2 | Virtual linebuffers for image signal processors | Physics | 2 | Active |
| US9286216B2 | 3DIC memory chips including computational logic-in-memory for performing accelerated data processing | Emerging Cross-Sectional Technologies | 2 | Active |
| US10685422B2 | Compiler managed memory for image processor | Physics | 1 | Active |
| US10275253B2 | Energy efficient processor core architecture for image processor | Electricity | 1 | Active |
| US10397450B2 | Two dimensional shift array for image processor | Physics | 0 | Active |
| US11140293B2 | Sheet generator for image processor | Physics | 0 | Active |
| US11153464B2 | Two dimensional shift array for image processor | Physics | 0 | Active |
| US10638073B2 | Line buffer unit for image processor | Electricity | 0 | Active |
| US10791284B2 | Virtual linebuffers for image signal processors | Physics | 0 | Active |
| US10216487B2 | Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure | Physics | 0 | Active |
| US10430919B2 | Determination of per line buffer unit memory allocation | Emerging Cross-Sectional Technologies | 0 | Active |
| US10685423B2 | Determination of per line buffer unit memory allocation | Emerging Cross-Sectional Technologies | 0 | Active |
| US10560598B2 | Sheet generator for image processor | Physics | 0 | Active |
| US10872393B2 | Image processor with high throughput internal communication protocol | Electricity | 0 | Active |
| US11138013B2 | Energy efficient processor core architecture for image processor | Electricity | 0 | Active |
| US10095479B2 | Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.