Processing array device that performs one cycle full adder operation and bit line read/write logic features
US10877731B1 · kind B1 · utility
17Cited by
271References
27Claims
0Family size
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Key dates
| Filing date | Jun 18, 2019 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Jun 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/21
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing array that performs one cycle full adder operations. The processing array may have different bit line read/write logic that permits different operations to be performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.