Multi-level signaling scheme for memory interface
US10878860B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 27, 2019 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Dec 27, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage system includes a memory including a plurality of memory cells; and an interface coupled to the memory and a host. The interface includes a multi-level transmission encoder configured to receive an input data signal from the host and encode the input data signal as a multi-level data signal. The interface further includes a multi-stage driver network including a plurality of driver stages, wherein each driver stage of the plurality of driver stages is configured to apply an impedance or forego applying an impedance to the multi-level data signal based on a previous state and a current state of the multi-level data signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.