Patent · US Active

Control architecture for column decoder circuitry

US10878893B1 · kind B1 · utility

0Cited by

5References

23Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Vianney Choserot · Antibes, FR
Andy Wangkun Chen · Austin, US
Sriram Thyagarajan · Austin, US
Yew Keong Chong · Austin, US
Munish Kumar · Sindhar, IN

Key dates

Filing date	Jun 4, 2019
Grant date	Dec 29, 2020
Priority date	—
Expiry date	Jun 4, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH10B10/12
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to memory circuitry having an array of bitcells and bitlines coupled to columns of the bitcells. Also, column decoder circuitry may be coupled to the bitcells via the bitlines, and the column decoder circuitry may have read logic coupled to an output node. The column decoder circuitry may have select logic coupled between a voltage supply and the read logic. Enable signals may be used to activate the select logic to pass the voltage supply to the read logic, and the bitlines provide bitline signals that activate the read logic to pass the voltage supply from the select logic to the output node.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.