Resistive address decoder and virtually addressed memory
US10878906B2 · kind B2 · utility
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6Claims
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Key dates
| Filing date | Feb 13, 2018 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | Feb 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
NAND-based content addressable memory is provided with a memory cell including two programmable resistive elements, such as memristors. These memory cells can be used to provide a programmable resistive address decoder. Such decoders can improve computer hardware performance in various ways: 1) improved translation lookaside buffers, 2) improved cache memory, and 3) by eliminating physical addresses entirely.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.