Techniques for controlling transistor sub-fin leakage

US10879241B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Glenn A. Glass · Portland, US
• Prashant Majhi · San Jose, US
• Anand S. Murthy · Beaverton, US
• Tahir Ghani · Portland, US
• Daniel B. Aubertine · North Plains, US
• Heidi M. Meyer · Hillsboro, US
• Karthik Jambunathan · Hillsboro, US
• Gopinath Bhimarasetti · Portland, US

Key dates

• Filing date: Sep 25, 2015
• Grant date: Dec 29, 2020
• Expiry date: Sep 25, 2035

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/017
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Techniques are disclosed for controlling transistor sub-fin leakage. The techniques can be used for highly scaled finFETs, as well as other non-planar transistors. In some cases, the techniques include exposing a middle portion of a fin structure formed on a substrate and then converting the exposed portion to an electrically isolating material via a doping or oxidation process. For example, a monolayer doping (MLD) process may be used to deliver dopants to the exposed portion of the fin in a self-saturated monolayer scheme. In another example case, thermal oxidation may be used to convert the exposed portion to an insulator material. In some cases, a barrier layer (e.g., including carbon doping) may be located above the exposed portion of the fin to help prevent the doping or oxidation process from affecting the upper region of the fin, which is used for the transistor channel.