Three-dimensional memory devices with architecture of increased number of bit lines
US10879263B2 · kind B2 · utility
1Cited by
3References
20Claims
0Family size
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Key dates
| Filing date | May 3, 2019 |
| Grant date | Dec 29, 2020 |
| Priority date | — |
| Expiry date | May 3, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a three-dimensional (3D) memory device are disclosed. The 3D memory device has an architecture with an increased number of bit lines. In an example, the 3D memory device includes a substrate, a plurality of memory strings each extending vertically above the substrate in a memory region, and a plurality of bit lines over the plurality of memory strings. At least one of the plurality of bit lines is electrically connected to a single one of the plurality of memory strings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.