SRAM with error correction in retention mode
US10885972B2 · kind B2 · utility
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5References
20Claims
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Key dates
| Filing date | Mar 27, 2020 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | Mar 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for storing information in SRAM bit cell arrays provides for lowering voltage supplied to the SRAM bit cell arrays, with voltage lowering controlled by a connected voltage control circuit. Writing, reading, and correcting information storable in the SRAM bit cell arrays is accomplished using an error correcting code (ECC) block connected to at least some of the SRAM bit cell arrays. The ECC block is configurable to repair stored information.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.