Semiconductor die with improved ruggedness
US10886189B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 2019 |
| Grant date | Jan 5, 2021 |
| Priority date | — |
| Expiry date | May 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/8503
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor die includes a substrate, a first passivation layer over the substrate, and a second passivation layer over the first passivation layer and the substrate. The substrate has boundaries defined by a substrate termination edge. The first passivation layer is over the substrate such that it terminates at a first passivation termination edge that is inset from the substrate termination edge by a first distance. The second passivation layer is over the first passivation layer and the substrate such that it terminates at a second passivation termination edge that is inset from the substrate termination edge by a second distance. The second distance is less than the first distance such that the second passivation layer overlaps the first passivation layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.