Integrated circuit device with back-side interconnection to deep source/drain semiconductor

US10886217B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Patrick Morrow · Portland, US
• Mauro J. Kobrinsky · Portland, US
• Mark Bohr · Beaverton, US
• Tahir Ghani · Portland, US
• Rishabh Mehandru · Portland, US

Key dates

• Filing date: Dec 23, 2016
• Grant date: Jan 5, 2021
• Expiry date: Jan 27, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D89/10
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Transistor cell architectures including both front-side and back-side structures. A transistor may include one or more semiconductor fins with a gate stack disposed along a sidewall of a channel portion of the fin. One or more source/drain regions of the fin are etched to form recesses with a depth below the channel region. The recesses may extend through the entire fin height. Source/drain semiconductor is then deposited within the recess, coupling the channel region to a deep source/drain. A back-side of the transistor is processed to reveal the deep source/drain semiconductor material. One or more back-side interconnect metallization levels may couple to the deep source/drain of the transistor.