Power saving scannable latch output driver
US10890623B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2019 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Sep 4, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0016
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Techniques for a power saving scannable latch output driver in an integrated circuit (IC) are described herein. An aspect includes receiving, by a circuit comprising a scannable latch, a scan signal. Another aspect includes, based on the scan signal being enabled, turning on a scan output driver of the scannable latch, wherein a scan input of the scannable latch propagates through the scannable latch to a scan output based on the scan output driver being turned on. Another aspect includes, based on the scan signal being disabled, turning off the scan output driver, wherein the scan output driver comprises a first p-type field effect transistor (PFET) and a first n-type field effect transistor (NFET), wherein a gate of the first PFET and a gate of the first NFET are connected to an output of a latch of the scannable latch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.