Daniel Rodko
19Patents
3h-index
21Co-inventors
56Inventor score
Filing activity: May 11, 2004 → Sep 17, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US7257745B2 | Array self repair using built-in self test techniques | Physics | 12 | Expired |
| US7305602B2 | Merged MISR and output register without performance impact for circuits under test | Physics | 5 | Expired |
| US7478297B2 | Merged MISR and output register without performance impact for circuits under test | Physics | 5 | Active |
| US9627012B1 | Shift register with opposite shift data and shift clock directions | Physics | 3 | Active |
| US8327207B2 | Memory testing system | Physics | 2 | Active |
| US10079070B2 | Testing content addressable memory and random access memory | Physics | 1 | Active |
| US9697910B1 | Multi-match error detection in content addressable memory testing | Physics | 1 | Active |
| US10170199B2 | Testing content addressable memory and random access memory | Physics | 1 | Active |
| US10971242B2 | Sequential error capture during memory test | Physics | 1 | Active |
| US10593420B2 | Testing content addressable memory and random access memory | Physics | 1 | Active |
| US10998075B2 | Built-in self-test for bit-write enabled memory arrays | Physics | 1 | Active |
| US10890623B1 | Power saving scannable latch output driver | Electricity | 1 | Active |
| US10288684B2 | On-chip hardware-controlled window strobing | Physics | 0 | Active |
| US7536613B2 | BIST address generation architecture for multi-port memories | Physics | 0 | Expired |
| US7275194B2 | Clock duty cycle based access timer combined with standard stage clocked output register | Physics | 0 | Expired |
| US11657887B2 | Testing bit write operation to a memory array in integrated circuits | Physics | 0 | Active |
| US10281527B2 | On-chip hardware-controlled window strobing | Physics | 0 | Active |
| US9983261B2 | Partition-able storage of test results using inactive storage elements | Physics | 0 | Active |
| US11462295B2 | Microchip level shared array repair | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.