Pradip Patel
23Patents
5h-index
27Co-inventors
69Inventor score
Filing activity: May 31, 1995 → Sep 11, 2019
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5659551A | Programmable computer system element with built-in self test method and apparatus for repair during power-on | Physics | 87 | Expired |
| US5805789A | Programmable computer system element with built-in self test method and apparatus for repair during power-on | Physics | 32 | Expired |
| US5633877A | Programmable built-in self test method and controller for arrays | Physics | 30 | Expired |
| US7257745B2 | Array self repair using built-in self test techniques | Physics | 12 | Expired |
| US8055960B2 | Self test apparatus for identifying partially defective memory | Physics | 9 | Active |
| US7305602B2 | Merged MISR and output register without performance impact for circuits under test | Physics | 5 | Expired |
| US7478297B2 | Merged MISR and output register without performance impact for circuits under test | Physics | 5 | Active |
| US7529997B2 | Method for self-correcting cache using line delete, data logging, and fuse repair correction | Physics | 4 | Active |
| US9627012B1 | Shift register with opposite shift data and shift clock directions | Physics | 3 | Active |
| US7366953B2 | Self test method and apparatus for identifying partially defective memory | Physics | 3 | Expired |
| US8327207B2 | Memory testing system | Physics | 2 | Active |
| US6629280B1 | Method and apparatus for delaying ABIST start | Physics | 2 | Expired |
| US10890623B1 | Power saving scannable latch output driver | Electricity | 1 | Active |
| US10998075B2 | Built-in self-test for bit-write enabled memory arrays | Physics | 1 | Active |
| US9697910B1 | Multi-match error detection in content addressable memory testing | Physics | 1 | Active |
| US10079070B2 | Testing content addressable memory and random access memory | Physics | 1 | Active |
| US10593420B2 | Testing content addressable memory and random access memory | Physics | 1 | Active |
| US10971242B2 | Sequential error capture during memory test | Physics | 1 | Active |
| US10170199B2 | Testing content addressable memory and random access memory | Physics | 1 | Active |
| US7536613B2 | BIST address generation architecture for multi-port memories | Physics | 0 | Expired |
| US9983261B2 | Partition-able storage of test results using inactive storage elements | Physics | 0 | Active |
| US7275194B2 | Clock duty cycle based access timer combined with standard stage clocked output register | Physics | 0 | Expired |
| US8361776B2 | Adaptation of Pitman Moore strain of rabies virus to primary chick embryo fibroblast cell cultures | Chemistry; Metallurgy | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.