Bit-line repeater insertion architecture
US10891992B1 · kind B1 · utility
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6References
21Claims
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Key dates
| Filing date | Feb 14, 2018 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Feb 14, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SRAM architecture to optimize the performance of the SRAM. The local bit-lines are activated one at a time with control signals from a decoder. The global bit-lines are broken with repeaters to optimize performance. This guarantees optimal performance for the SRAM array across a wide range of supply voltages spanning from the nominal voltage of a process to a sub-threshold range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.