Three-dimensional memory device programming with reduced disturbance
US10892023B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 15, 2019 |
| Grant date | Jan 12, 2021 |
| Priority date | — |
| Expiry date | Aug 16, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/845
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of 3D memory devices and methods for operating the 3D memory devices are disclosed. In an example, a method for operating a 3D memory device is disclosed. The 3D memory device includes memory decks each including memory layers in a vertical direction. Each memory layer in a first memory deck is first programmed. The first programming includes applying a program voltage to the memory layer and a first channel pass voltage smaller than the program voltage to each rest of the memory layers. Each memory layer in a second memory deck above the first memory deck is second programmed. The second programming includes applying the program voltage to the memory layer and the first channel pass voltage to each rest of the memory layers. The second programming further includes applying a second channel pass voltage smaller than the first channel pass voltage to each memory layer in the first memory deck.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.